(* Copyright Per Lindgren 2014, see the file "LICENSE" *)
(* for the full license governing this code.           *)

(* RTFM-core/IsrVector *)

type isr_type =
  | K (* reserved by the RTFM kernel                *)
  | R (* reserved by ARM                            *) 
  | O (* overridable but has default implementation *)
  | F (* free to use by the application             *)
  | U (* used by the application                    *)
    
let isr_vector = [
    (* Core Level - CM3 *)
    (K, "&_vStackTop");                            (* The initial stack pointer *)
    (K, "_reset_handler");                         (* The reset handler *)
    (O, "_nmi_handler");                           (* The NMI handler *)
    (O, "_hard_fault_handler");                    (* The hard fault handler *)
    (O, "_memory_management_fault_handler");       (* The MPU fault handler *)
    (O, "_bus_fault_handler");                     (* The bus fault handler *)
    (O, "_usage_fault_handler");                   (* The usage fault handler *)
    (R, "0");                                      (* Reserved *)
    (R, "0");                                      (* Reserved *)
    (R, "0");                                      (* Reserved *)
    (R, "0");                                      (* Reserved *)
    (O, "_svc_handler");                           (* SVCall handler *)
    (O, "_debug_monitor_handler");                 (* Debug monitor handler *)
    (R, "0");                                      (* Reserved *)
    (O, "_pend_sv_handler");                       (* The PendSV handler *)
    (O, "_systick_handler");                       (* The SysTick handler *)

    (* Chip Level - Freescale *)
    (F, "_isr_dma0");                              (* DMA channel  0 transfer complete *)
    (F, "_isr_dma1");                              (* DMA channel  1 transfer complete *)
    (F, "_isr_dma2");                              (* DMA channel  2 transfer complete *)
    (F, "_isr_dma3");                              (* DMA channel  3 transfer complete *)
    (F, "_isr_dma4");                              (* DMA channel  4 transfer complete *)
    (F, "_isr_dma5");                              (* DMA channel  5 transfer complete *)
    (F, "_isr_dma6");                              (* DMA channel  6 transfer complete *)
    (F, "_isr_dma7");                              (* DMA channel  7 transfer complete *)
    (F, "_isr_dma8");                              (* DMA channel  8 transfer complete *)
    (F, "_isr_dma9");                              (* DMA channel  9 transfer complete *)
    (F, "_isr_dma10");                             (* DMA channel 10 transfer complete *)
    (F, "_isr_dma11");                             (* DMA channel 11 transfer complete *)
    (F, "_isr_dma12");                             (* DMA channel 12 transfer complete *)
    (F, "_isr_dma13");                             (* DMA channel 13 transfer complete *)
    (F, "_isr_dma14");                             (* DMA channel 14 transfer complete *)
    (F, "_isr_dma15");                             (* DMA channel 15 transfer complete *)
    (F, "_isr_dma_error");                         (* DMA Error Interrupt *)
    (F, "_isr_mcm");                               (* Normal Interrupt *)
    (F, "_isr_flash_cmd_complete");                (* FTFL Interrupt *)
    (F, "_isr_flash_read_collision");              (* Read Collision Interrupt *)
    (F, "_isr_mode_controller");                   (* Low Voltage Detect/Warning *)
    (F, "_isr_low_leakage_wakeup");                (* Low Leakage Wakeup *)
    (F, "_isr_watchdog");                          (* WDOG Interrupt *)
    (F, "_isr_random_number_generator");           (* RNGB Interrupt *)
    (F, "_isr_i2c0");                              (* I2C0 Interrupt *)
    (F, "_isr_i2c1");                              (* I2C1 Interrupt *)
    (F, "_isr_spi0");                              (* SPI0 Interrupt *)
    (F, "_isr_spi1");                              (* SPI1 Interrupt *)
    (F, "_isr_spi2");                              (* SPI2 Interrupt *)
    (F, "_isr_can0_ored_msg_buffer");              (* CAN0 OR'd Message Buffers Interrupt *)
    (F, "_isr_can0_buffer_off");                   (* CAN0 Bus Off Interrupt *)
    (F, "_isr_can0_error");                        (* CAN0 Error Interrupt *)
    (F, "_isr_can0_tx_warning");                   (* CAN0 Tx Warning Interrupt *)
    (F, "_isr_can0_rx_warning");                   (* CAN0 Rx Warning Interrupt *)
    (F, "_isr_can0_wake_up");                      (* CAN0 Wake Up Interrupt *)
    (F, "_isr_can0_imeu");                         (* Reserved interrupt 51 *)
    (F, "_isr_can0_lost_rx");                      (* Reserved interrupt 52 *)
    (F, "_isr_can1_ored_msg_buffer");              (* CAN1 OR'd Message Buffers Interrupt *)
    (F, "_isr_can1_buffer_off");                   (* CAN1 Bus Off Interrupt *)
    (F, "_isr_can1_error");                        (* CAN1 Error Interrupt *)
    (F, "_isr_can1_tx_warning");                   (* CAN1 Tx Warning Interrupt *)
    (F, "_isr_can1_rx_warning");                   (* CAN1 Rx Warning Interrupt *)
    (F, "_isr_can1_wake_up");                      (* CAN1 Wake Up Interrupt *)
    (F, "_isr_can1_imeu");                         (* Reserved interrupt 59 *)
    (F, "_isr_can1_lost_rx");                      (* Reserved interrupt 60 *)
    (F, "_isr_uart0_status_sources");              (* UART0 Receive/Transmit interrupt *)
    (F, "_isr_uart0_error_sources");               (* UART0 Error interrupt *)
    (F, "_isr_uart1_status_sources");              (* UART1 Receive/Transmit interrupt *)
    (F, "_isr_uart1_error_sources");               (* UART1 Error interrupt *)
    (F, "_isr_uart2_status_sources");              (* UART2 Receive/Transmit interrupt *)
    (F, "_isr_uart2_error_sources");               (* UART2 Error interrupt *)
    (F, "_isr_uart3_status_sources");              (* UART3 Receive/Transmit interrupt *)
    (F, "_isr_uart3_error_sources");               (* UART3 Error interrupt *)
    (F, "_isr_uart4_status_sources");              (* UART4 Receive/Transmit interrupt *)
    (F, "_isr_uart4_error_sources");               (* UART4 Error interrupt *)
    (F, "_isr_uart5_status_sources");              (* UART5 Receive/Transmit interrupt *)
    (F, "_isr_uart5_error_sources");               (* UART5 Error interrupt *)
    (F, "_isr_adc0");                              (* ADC0 interrupt *)
    (F, "_isr_adc1");                              (* ADC1 interrupt *)
    (F, "_isr_cmp0");                              (* CMP0 interrupt *)
    (F, "_isr_cmp1");                              (* CMP1 interrupt *)
    (F, "_isr_cmp2");                              (* CMP2 interrupt *)
    (F, "_isr_ftm0");                              (* FTM0 fault, overflow and channels interrupt *)
    (F, "_isr_ftm1");                              (* FTM1 fault, overflow and channels interrupt *)
    (F, "_isr_ftm2");                              (* FTM2 fault, overflow and channels interrupt *)
    (F, "_isr_cmt");                               (* CMT interrupt *)
    (F, "_isr_rtc_alarm");                         (* RTC interrupt *)
    (F, "_isr_rtc_seconds");                       (* Reserved interrupt 83 *)
    (F, "_isr_pit0");                              (* PIT timer channel 0 interrupt *)
    (F, "_isr_pit1");                              (* PIT timer channel 1 interrupt *)
    (F, "_isr_pit2");                              (* PIT timer channel 2 interrupt *)
    (F, "_isr_pit3");                              (* PIT timer channel 3 interrupt *)
    (F, "_isr_pdb");                               (* PDB0 Interrupt *)
    (F, "_isr_usb_otg");                           (* USB0 interrupt *)
    (F, "_isr_usb_charger_detect");                (* USBDCD Interrupt *)
    (F, "_isr_ethernet_mac_1588_timer");           (* Ethernet MAC IEEE 1588 Timer Interrupt *)
    (F, "_isr_ethernet_mac_tx");                   (* Ethernet MAC Transmit Interrupt *)
    (F, "_isr_ethernet_mac_rx");                   (* Ethernet MAC Receive Interrupt *)
    (F, "_isr_ethernet_mac_error");                (* Ethernet MAC Error and miscelaneous Interrupt *)
    (F, "_isr_i2s");                               (* I2S0 Interrupt *)
    (F, "_isr_sdhc");                              (* SDHC Interrupt *)
    (F, "_isr_dac0");                              (* DAC0 interrupt *)
    (F, "_isr_dac1");                              (* DAC1 interrupt *)
    (F, "_isr_tsi");                               (* TSI0 Interrupt *)
    (F, "_isr_mcg");                               (* MCG Interrupt *)
    (F, "_isr_low_power_timer");                   (* LPTimer interrupt *)
    (F, "_isr_gpio_a");                            (* Reserved interrupt 102 *)
    (F, "_isr_gpio_b");                            (* Port A interrupt *)
    (F, "_isr_gpio_c");                            (* Port B interrupt *)
    (F, "_isr_gpio_d");                            (* Port C interrupt *)
    (F, "_isr_gpio_e");                            (* Port D interrupt *)
    (F, "_isr_software");                          (* Port E interrupt *)
]
    
let isr_maxpri = 32

      
